'Processor Brand String Feature' is not supported Now we look at the output from the CPUID instruction... CPU Vendor ID: 'GenuineIntel' Number of CPUID EAX tests: 3 The Brand ID (0x00) is Unsupported This processor has the following EDX feature flags: FPU - Floating-point unit on-Chip; The processor contains an FPU that supports the Intel387 floating-point instruction set. VME - Virtual Mode Extension; The processor supports extensions to virtual-8086 mode. DE - Debugging Extension; The processor supports I/O breakpoints, including the CR4.DE bit for enabling debug extensions and optional trapping of access to the DR4 and DR5 registers. PSE - Page Size Extension; The processor supports 4-Mbyte pages. TSC - Time Stamp Counter; The RDTSC instruction is supported including the CR4.TSD bit for access/privilege control. MSR - Model Specific Registers; Model Specific Registers are implemented with the RDMSR, WRMSR instructions PAE - Physical Address Extension; Physical addresses greater than 32 bits are supported. MCE - Machine Check Exception; Machine Check Exception, Exception 18, and the CR4.MCE enable bit are supported CX8 - CMPXCHG8 Instruction Supported; The compare and exchange 8 bytes instruction is supported. APIC - On-chip APIC Hardware Supported; The processor contains a software-accessible Local APIC. SEP - Fast System Call; Indicates whether the processor supports the Fast System Call instructions, SYSENTER and SYSEXIT. NOTE: Refer to Section 3.4 for further information regarding SYSENTER/ SYSEXIT feature and SEP feature bit. MTRR - Memory Type Range Registers; The Processor supports the Memory Type Range Registers specifically the MTRR_CAP register. PGE - Page Global Enable; The global bit in the page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature. MCA - Machine Check Architecture; The Machine Check Architecture is supported, specifically the MCG_CAP register. CMOV - Conditional Move Instruction Supported; The processor supports CMOVcc, and if the FPU feature flag (bit 0) is also set, supports the FCMOVCC and FCOMI instructions. PAT - Page Attribute Table; Indicates whether the processor supports the Page Attribute Table. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on 4K granularity through a linear address. PSE-36 - 36-bit Page Size Extension; Indicates whether the processor supports 4-Mbyte pages that are capable of addressing physical memory beyond 4GB. This feature indicates that the upper four bits of the physical address of the 4-Mbyte page is encoded by bit 13-16 of the page directory entry. NOT SUPPORTED: PSN - Processor serial number is present and enabled; The processor supports the 96-bit processor serial number feature, and the feature is enabled. NOT SUPPORTED: CLFSH - CLFLUSH Instruction supported; Indicates that the processor supports the CLFLUSH instruction. NOT SUPPORTED: DS - Debug Store; Indicates that the processor has the ability to write a history of the branch to and from addresses into a memory buffer. NOT SUPPORTED: ACPI - Thermal Monitor and Software Controlled Clock Facilities supported; The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control. MMX - Intel Architecture MMX technology supported; The processor supports the MMX technology instruction set extensions to Intel Architecture. FXSR - Fast floating point save and restore; Indicates whether the processor supports the FXSAVE and FXRSTOR instructions for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it uses the fast save/restore instructions. NOT SUPPORTED: SSE - Streaming SIMD Extensions supported; The processor supports the Streaming SIMD Extensions to the Intel Architecture. NOT SUPPORTED: SSE2 - Streaming SIMD Extensions 2; Indicates the processor supports the Streaming SIMD Extensions - 2 Instructions. NOT SUPPORTED: SS - Self-Snoop; The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. NOT SUPPORTED: HTT - Hyper-Threading Technology; This processor’s microarchitecture has the capability to operate as multiple logical processors within the same physical package. This field does not indicate that Hyper-Threading Technology has been enabled for this specific processor. To determine if Hyper-Threading Technology is supported, check the value returned in EBX[23:16] after executing CPUID with EAX=1. If EBX[23:16] contains a value >1, then the processor supports Hyper-Threading Technology. NOT SUPPORTED: TM - Thermal Monitor supported; The processor implements the Thermal Monitor automatic thermal control circuit (TCC). NOT SUPPORTED: SBF - Signal Break on FERR; The processor supports the Signal Break on FERR feature. The FERR signal is asserted if an interrupt is pending and STPCLK is asserted. This processor has the following ECX feature flags: NOT SUPPORTED: SSE3 - Streaming SIMD Extensions 3; The processor supports the Streaming SIMD Extensions 3 instructions. NOT SUPPORTED: MONITOR - MONITOR/MWAIT; The processor supports the MONITOR and MWAIT instructions. NOT SUPPORTED: DS-CPL - CPL Qualified Debug Store; The processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL. NOT SUPPORTED: EST - Enhanced Intel SpeedStep technology; The processor implements the second-generation Intel SpeedStep technology feature. NOT SUPPORTED: TM2 - Thermal Monitor 2; The processor implements the Thermal Monitor 2 thermal control circuit (TCC). NOT SUPPORTED: CID - Context ID; The L1 data cache mode can be set to either adaptive mode or shared mode by the BIOS. Processor Signature:(bin EAX: 00000000000000000000011001010010)(hex EAX: 00000652) Stepping: 0010 Model: 0101 Family: 0110 Type: 00 ExMod: 0000 ExFam: 00000000 Cache and TLB information: Instruction TLB: 4-KBPages, 4-way set associative, 32 entries Instruction TLB: 4-MB Pages, fully associative, 2 entries Data TLB: 4-KB Pages, 4-way set associative, 64 entries 2nd-level cache: 512-KB, 4-way set associative, 32 byte line size 1st-level instruction cache: 16-KB, 4-way set associative, 32-byte line size Data TLB: 4-MB Pages, 4-way set associative, 8 entries 1st-level data cache: 16-KB, 4-way set associative, 32-byte line size