/*********************************************
    SelfModifyingCPUID.c
    Written by Keith Oxenrider
    koxenrider[at]sol[dash]biotech[dot]com
    January 25, 2005 (my boy is 3 months old today!)

    This code is hereby placed in the public domain.
    No warrenty expressed or implied, use at your own risk!


    The information for decoding the CPUID data
    was taken from the Feb 2004 Intel document
    "Intel® Processor Identification and the CPUID Instruction"
    AP-485 (file name 24161825.pdf)

    No test is made to determine if the CPUID instruction
    is valid; it is available on all processors 486 and up.
*********************************************/

#define MAXCPUIDTESTS 4

#define FALSE 0
#define TRUE  1

typedef unsigned char BOOL;


BOOL boolHasCLFLUSHInstr = FALSE;
BOOL boolIsHyperThreaded = FALSE;
BOOL boolIsP4orHigher = FALSE;

struct VALSTR{
    unsigned int val;
    char *descr;
};

#define BrandIDCnt 16
const int BrandIDs[BrandIDCnt] = {
    0x00,
    0x01,
    0x02,
    0x03,
    0x04,
    0x06,
    0x07,
    0x08,
    0x09,
    0x0A,
    0x0B,
    0x0C,
    0x0E,
    0x0F,
    0x13,
    0x16
};

const char *BrandStr[BrandIDCnt+1] = {
    "Unsupported",
    "Intel Celeron processor",
    "Intel Pentium III processor",
    "Intel Pentium III Xeon processor If processor signature = 000006B1h, then \"Intel Celeron processor\"",
    "Intel Pentium III processor",
    "Mobile Intel Pentium III Processor-M",
    "Mobile Intel Celeron processor",
    "Intel Pentium 4 processor If processor signature is >=00000F13h, then \"Intel Genuine processor\"",
    "Intel Pentium 4 processor",
    "Intel Celeron Processor",
    "Intel Xeon processor If processor signature is <00000F13h, then \"Intel Xeon processor MP\"",
    "Intel Xeon processor MP",
    "Mobile Intel Pentium 4 processor-M If processor signature is <00000F13h, then \"Intel Xeon processor\"",
    "Mobile Intel Celeron Processor",
    "Mobile Intel Celeron processor",
    "Intel Pentium M processor",
    "Reserved"
};


const char *EDXFeatureFlags[32] = {
    "FPU - Floating-point unit on-Chip; The processor contains an FPU that supports the Intel387 floating-point instruction set.",
    "VME - Virtual Mode Extension; The processor supports extensions to virtual-8086 mode.",
    "DE - Debugging Extension; The processor supports I/O breakpoints, including the CR4.DE bit for enabling debug extensions and optional trapping of access to the DR4 and DR5 registers.",
    "PSE - Page Size Extension; The processor supports 4-Mbyte pages.",
    "TSC - Time Stamp Counter; The RDTSC instruction is supported including the CR4.TSD bit for access/privilege control.",
    "MSR - Model Specific Registers; Model Specific Registers are implemented with the RDMSR, WRMSR instructions",
    "PAE - Physical Address Extension; Physical addresses greater than 32 bits are supported.",
    "MCE - Machine Check Exception; Machine Check Exception, Exception 18, and the CR4.MCE enable bit are supported",
    "CX8 - CMPXCHG8 Instruction Supported; The compare and exchange 8 bytes instruction is supported.",
    "APIC - On-chip APIC Hardware Supported; The processor contains a software-accessible Local APIC.",
    "Reserved Do not count on their value.",
    "SEP - Fast System Call; Indicates whether the processor supports the Fast System Call instructions, SYSENTER and SYSEXIT. NOTE: Refer to Section 3.4 for further information regarding SYSENTER/ SYSEXIT feature and SEP feature bit.",
    "MTRR - Memory Type Range Registers; The Processor supports the Memory Type Range Registers specifically the MTRR_CAP register.",
    "PGE - Page Global Enable; The global bit in the page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.",
    "MCA - Machine Check Architecture; The Machine Check Architecture is supported, specifically the MCG_CAP register.",
    "CMOV - Conditional Move Instruction Supported; The processor supports CMOVcc, and if the FPU feature flag (bit 0) is also set, supports the FCMOVCC and FCOMI instructions.",
    "PAT - Page Attribute Table; Indicates whether the processor supports the Page Attribute Table. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on 4K granularity through a linear address.",
    "PSE-36 - 36-bit Page Size Extension; Indicates whether the processor supports 4-Mbyte pages that are capable of addressing physical memory beyond 4GB. This feature indicates that the upper four bits of the physical address of the 4-Mbyte page is encoded by bit 13-16 of the page directory entry.",
    "PSN - Processor serial number is present and enabled; The processor supports the 96-bit processor serial number feature, and the feature is enabled.",
    "CLFSH - CLFLUSH Instruction supported; Indicates that the processor supports the CLFLUSH instruction.",
    "Reserved Do not count on their value.",
    "DS - Debug Store; Indicates that the processor has the ability to write a history of the branch to and from addresses into a memory buffer.",
    "ACPI - Thermal Monitor and Software Controlled Clock Facilities supported; The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.",
    "MMX - Intel Architecture MMX technology supported; The processor supports the MMX technology instruction set extensions to Intel Architecture.",
    "FXSR - Fast floating point save and restore; Indicates whether the processor supports the FXSAVE and FXRSTOR instructions for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it uses the fast save/restore instructions.",
    "SSE - Streaming SIMD Extensions supported; The processor supports the Streaming SIMD Extensions to the Intel Architecture.",
    "SSE2 - Streaming SIMD Extensions 2; Indicates the processor supports the Streaming SIMD Extensions - 2 Instructions.",
    "SS - Self-Snoop; The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.",
    "HTT - Hyper-Threading Technology; This processor’s microarchitecture has the capability to operate as multiple logical processors within the same physical package. This field does not indicate that Hyper-Threading Technology has been enabled for this specific processor. To determine if Hyper-Threading Technology is supported, check the value returned in EBX[23:16] after executing CPUID with EAX=1. If EBX[23:16] contains a value >1, then the processor supports Hyper-Threading Technology.",
    "TM - Thermal Monitor supported; The processor implements the Thermal Monitor automatic thermal control circuit (TCC).",
    "Reserved Do not count on their value.",
    "SBF - Signal Break on FERR; The processor supports the Signal Break on FERR feature. The FERR signal is asserted if an interrupt is pending and STPCLK is asserted."
};

const char *ECXFeatureFlags[32] = {
    "SSE3 - Streaming SIMD Extensions 3; The processor supports the Streaming SIMD Extensions 3 instructions.",
    "Reserved - Do not count on their value.",
    "Reserved - Do not count on their value.",
    "MONITOR - MONITOR/MWAIT; The processor supports the MONITOR and MWAIT instructions.",
    "DS-CPL - CPL Qualified Debug Store; The processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "EST - Enhanced Intel SpeedStep technology; The processor implements the second-generation Intel SpeedStep technology feature.",
    "TM2 - Thermal Monitor 2; The processor implements the Thermal Monitor 2 thermal control circuit (TCC).",
    "Reserved Do not count on their value.",
    "CID - Context ID; The L1 data cache mode can be set to either adaptive mode or shared mode by the BIOS.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value.",
    "Reserved Do not count on their value."
};

#define CacheTLBCnt 49
const struct VALSTR CacheTLB[CacheTLBCnt] = {
    {0x00, "Null"},
    {0x01, "Instruction TLB: 4-KBPages, 4-way set associative, 32 entries"},
    {0x02, "Instruction TLB: 4-MB Pages, fully associative, 2 entries"},
    {0x03, "Data TLB: 4-KB Pages, 4-way set associative, 64 entries"},
    {0x04, "Data TLB: 4-MB Pages, 4-way set associative, 8 entries"},
    {0x06, "1st-level instruction cache: 8-KB, 4-way set associative, 32-byte line size"},
    {0x08, "1st-level instruction cache: 16-KB, 4-way set associative, 32-byte line size"},
    {0x0A, "1st-level data cache: 8-KB, 2-way set associative, 32-byte line size"},
    {0x0C, "1st-level data cache: 16-KB, 4-way set associative, 32-byte line size"},
    {0x22, "3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64-byte line size"},
    {0x23, "3rd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x25, "3rd-level cache: 2-MB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x29, "3rd-level cache: 4-MB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x2C, "1st-level data cache: 32-KB, 8-way set associative, 64-byte line size"},
    {0x30, "1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size"},
    {0x39, "2nd-level cache: 128-KB, 4-way set associative, sectored cache, 64-byte line size"},
    {0x3B, "2nd-level cache: 128-KB, 2-way set associative, sectored cache, 64-byte line size"},
    {0x3C, "2nd-level cache: 256-KB, 4-way set associative, sectored cache, 64-byte line size"},
    {0x40, "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no3rd-level cache"},
    {0x41, "2nd-level cache: 128-KB, 4-way set associative, 32-byte line size"},
    {0x42, "2nd-level cache: 256-KB, 4-way set associative, 32-byte line size"},
    {0x43, "2nd-level cache: 512-KB, 4-way set associative, 32 byte line size"},
    {0x44, "2nd-level cache: 1-MB, 4-way set associative, 32 byte line size"},
    {0x45, "2nd-level cache: 2-MB, 4-way set associative, 32 byte line size"},
    {0x50, "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries"},
    {0x51, "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries"},
    {0x52, "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 256 entries"},
    {0x5B, "Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries"},
    {0x5C, "Data TLB: 4-KB or 4-MB pages, fully associative, 128 entries"},
    {0x5D, "Data TLB: 4-KB or 4-MB pages, fully associative, 256 entries"},
    {0x60, "1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x66, "1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size"},
    {0x67, "1st-level data cache: 16-KB, 4-way set associative, sectored cache, 64-byte line size"},
    {0x68, "1st-level data cache: 32-KB, 4 way set associative, sectored cache, 64-byte line size"},
    {0x70, "Trace cache: 12K-uops, 8-way set associative"},
    {0x71, "Trace cache: 16K-uops, 8-way set associative"},
    {0x72, "Trace cache: 32K-uops, 8-way set associative"},
    {0x79, "2nd-level cache: 128-KB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x7A, "2nd-level cache: 256-KB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x7B, "2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x7C, "2nd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size"},
    {0x82, "2nd-level cache: 256-KB, 8-way set associative, 32 byte line size"},
    {0x83, "2nd-level cache: 512-KB, 8-way set associative, 32 byte line size"},
    {0x84, "2nd-level cache: 1-MB, 8-way set associative, 32 byte line size"},
    {0x85, "2nd-level cache: 2-MB, 8-way set associative, 32 byte line size"},
    {0x86, "2nd-level cache: 512-KB, 4-way set associative, 64 byte line size"},
    {0x87, "2nd-level cache: 1-MB, 8-way set associative, 64 byte line size"},
    {0xB0, "Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries"},
    {0xB3, "Data TLB: 4-KB Pages, 4-way set associative, 128 entries"}
};